From 00a8c7546f46f8df2ee4dd3bc6457b057ed803fa Mon Sep 17 00:00:00 2001 From: Ain <41307858+nero@users.noreply.github.com> Date: Wed, 4 Apr 2018 22:35:09 +0000 Subject: [PATCH] Port uart driver to atmega32 --- drivers/uart.c | 7 +++--- drivers/uart.h | 55 +++++++++++++++++++++++++++++++++++++++++ drivers/uart_rx_async.c | 4 +-- drivers/uart_tx.c | 6 ++--- 4 files changed, 64 insertions(+), 8 deletions(-) diff --git a/drivers/uart.c b/drivers/uart.c index 16ab1ea..60e84e8 100644 --- a/drivers/uart.c +++ b/drivers/uart.c @@ -4,7 +4,8 @@ #define BAUD_PRESCALE (((F_CPU/(BAUDRATE*8UL)))-1) void __attribute__ ((naked)) __attribute__ ((section (".init5"))) uart_init() { - UCSR0A = (1<>8); + UBRRL = BAUD_PRESCALE; } diff --git a/drivers/uart.h b/drivers/uart.h index e69de29..7240143 100644 --- a/drivers/uart.h +++ b/drivers/uart.h @@ -0,0 +1,55 @@ +#ifndef U2X +#define U2X U2X0 +#endif + +#ifndef UCSZ0 +#define UCSZ0 UCSZ00 +#endif + +#ifndef UCSZ1 +#define UCSZ1 UCSZ01 +#endif + +#ifndef TXEN +#define TXEN TXEN0 +#endif + +#ifndef RXEN +#define RXEN RXEN0 +#endif + +#ifndef RXCIE +#define RXCIE RXCIE0 +#endif + +#ifndef UDRE +#define UDRE UDRE0 +#endif + +#ifndef UCSRA +#define UCSRA UCSR0A +#endif + +#ifndef UCSRB +#define UCSRB UCSR0B +#endif + +#ifndef UCSRC +#define UCSRC UCSR0C +#endif + +#ifndef UBRRH +#define UBRRH UBRR0H +#endif + +#ifndef UBRRL +#define UBRRL UBRR0L +#endif + +#ifndef UDR +#define UDR UDR0 +#endif + +#ifndef USART_RX_vect +#define USART_RX_vect USART_RXC_vect +#endif diff --git a/drivers/uart_rx_async.c b/drivers/uart_rx_async.c index 658b99f..381f753 100644 --- a/drivers/uart_rx_async.c +++ b/drivers/uart_rx_async.c @@ -4,7 +4,7 @@ #include void __attribute__ ((naked)) __attribute__ ((section (".init6"))) uart_rx_init() { - UCSR0B |= (1< void __attribute__ ((naked)) __attribute__ ((section (".init6"))) uart_tx_init() { - UCSR0B |= (1<